1. Field of the Invention
The present invention relates to the field of data storage devices, such as disk drives. More particularly, the present invention relates to a circuit and a method for detecting write-safe conditions for magnetic storage devices using magneto-resistive (MR) heads.
2. Description of the Related Art
FIG. 1 shows a schematic diagram of a conventional H-type write-driver circuit 10 having a conventional voltage-sense write-safe circuit 20. Write-driver circuit 10 is coupled to write element of an MR-type head 30 through electrical interconnect circuit 40. MR-type head 30 includes a write element 31 and an MR read element. Write element 31 is conventionally modelled by a capacitance C.sub.w that is in parallel to a series connection of a resistance R.sub.w and an inductance L.sub.w. Changes in current output by write-driver circuit 10 produces changes in magnetic flux at write element 31 that are recorded on a magnetic media, such as a tape or disk, in a well-known manner. Example of MR-type heads that can be used for head 30 are a Magneto-Resistive (MR) head, a Piggyback-Magneto-Resistive (PMR), and a Giant Magneto-Resistive (GMR) head (sometimes called spin valve head). Write-driver circuit 10 and write-safe circuit 20 are typically contained in a R/W integrated circuit (IC), represented by write-driver circuit 10 and write-safe circuit 20 being shown to the left of line 50. The components of FIG. 1 appearing to the right of line 50 are external to the R/W IC. The R/W IC is typically attached to the actuator used in a disk drive (not shown).
Write-safe circuit 20 is connected to the output of write-driver circuit 10 which detects the write conditions for reliably writing data to a magnetic tape or disk. A typical write-safe circuit 20, shown in FIG. 1, includes a buffer 21 coupled to the output of write-circuit 10. The output of buffer 21 is coupled to a write-safe logic circuit 22. Write-safe logic circuit 22 typically includes a comparator or a peak detection circuit for detecting write-safe conditions. Additionally, write-safe logic circuit 22 typically includes a timing circuit for detecting any improper I.sub.w transition rates at write element 31. Of the three write-safe conditions detected by write-safe circuits 20, two conditions are failure operational modes, while the third condition is a normal operational mode. The two failure operational modes are (1) a high ohmic, or open, connection to write element 31, and (2) a low ohmic, or short, connection to write element 31. Write-safe logic circuit provides a logic output for signalling detected write-safe conditions.
Write-driver circuit 10 includes transistors Q1-Q4 connected to write element 31 in a well-known H configuration. The collector-to-emitter paths of transistors Q1 and Q3 are connected in series to form a current path from a first power supply voltage V.sub.CC to a second power supply voltage V.sub.EE. Similarly, the collector-to-emitter paths of transistors Q2 and Q4 are connected in series to form a current path from V.sub.CC to V.sub.EE. Write element 31 is connected across the two current paths at the emitter-collector junction of transistors Q1 and Q3 and at the emittercollector junction of transistors Q2 and Q4.
Transistors Q3 and Q4 are driven by an input voltage V.sub.Win that is applied across inputs 11 and 12, respectively. Input voltage V.sub.Win causes transistors Q3 and Q4 to operate in a well-known complementary manner, that is, when transistor Q3 is conducting, transistor Q4 is non-conducting and, conversely, when transistor Q4 is conducting, transistor Q3 is non-conducting. The H configuration of transistors Q1-Q4 is configured so that transistor Q1 is non-conducting when transistor Q3 is conducting, but is conducting when transistor Q4 is conducting. Similarly, transistor Q2 is non-conducting when transistor Q4 is conducting, but is conducting when transistor Q3 is conducting. By changing the polarity of V.sub.Win applied across inputs 11 and 12, the direction of write current I.sub.w through write element 31 is controlled accordingly. Changes in the direction of I.sub.w cause changes in the magnetic flux produced at write element 31. The flux changes represent encoded data that are recorded on a magnetic media, such as a tape or disk, and that are later read back for retrieving the recorded data.
Parasitic capacitance at the output of a write-driver circuit limits the rate at which data can be written or stored for a magnetic storage device. The parasitic capacitance adversely affects the output performance of a write-driver, that is, the transition (rise and fall) times of the write current (I.sub.w) at the output of a write-driver are degraded. There are several sources contributing to the total parasitic capacitance appearing at the output of a conventional write-driver circuit. Four of the more significant sources of parasitic capacitance, as shown in FIG. 1, are write driver 10, write-safe circuit 20, write element 31 and electrical interconnect 40 between write-driver circuit 10 and write element 31.
Write-driver circuit 10 and write-safe circuit 20 contribute the most significant portion of the total parasitic capacitance appearing at the output of write-driver circuit 10. The parasitic capacitance contributed by write-driver circuit 10 is represented in FIG. 1 by C.sub.Par11 and C.sub.Par12. The parasitic capacitance contributed by write-safe circuit 20 is represented in FIG. 1 by C.sub.Par21 and C.sub.Par22. This portion of the parasitic capacitance, all associated with the R/W IC, is inherent to the active and passive semiconductor devices used within the IC and the electrical conductors connecting the circuit devices to the I/O pads of the R/W IC.
What is needed is a way to achieve faster I.sub.w current transitions so that faster data write rates can be achieved.